1. Field of the Invention
The present invention relates to an evaluation method of a characteristic parameter which is required in designing and manufacturing a field effect transistor. Specifically, the present invention relates to an evaluation method of an external resistance value of a field effect transistor having low concentration drain regions.
2. Description of the Related Art
A three-terminal element, referred generally to as a field effect transistor (FET), has a structure in which current is modulated to flow and controlled depending on an applied voltage to a terminal referred to as a gate electrode. The current path is referred to as a channel forming region, which is sandwiched between two impurity regions which are each referred to as a source region and a drain region. Among such FETs, a MOST (Metal Oxide Semiconductor Transistor), particularly a TFT (Thin Film Transistor), is employed widely as a main component of electronic devices such as a computer and a display.
Regarding application to an electronic device, a mode of using an FET as a switching element is employed widely. However, in this case, there is a problem that switching characteristics deteriorate as the amount of OFF (leakage) current of the FET increases. A so-called LDD (Lightly Doped Drain) structure having low concentration drain regions outside a channel forming region is generally employed as a method for suppressing the OFF (leakage) current. Optimization of the LDD resistance value and the length of the LDD region is required. In other words, optimization of LDD regions is important. It is effective for suppression of the OFF (leakage) current that the dopant density of the LDD region is reduced and the resistance value is increased. However, on the other hand, it leads to a problem that on-current or operating speed is reduced. Accordingly, in consideration of the advantages and the disadvantages, it is necessary to set an optimum LDD region. However, it is difficult to estimate a value of an external resistance (a resistance of the current path in the FET subtracting the resistance of the channel forming region) such as for an LDD region in a real FET.
Resistance values of drain, source and LDD regions can be controlled with the density or depth of one conductivity type impurity element such as boron or phosphorus and an activation method. A conventional FET structure, which has only a source region, a drain region and a channel forming region in an active layer, is well-researched and many appraisal methods are proposed. For example, a method for measuring a resistance value of a channel forming region and an external resistance value in a linear region is known. (For example, Reference 1: “submicron device II”, written by Mitsumasa Koyanagi, published by Maruzen Co., Ltd., Jan. 30, 1988, pp. 202–208.).
According to this method, the resistance value of a channel forming region (rch) which does not include the external resistance (r), is calculated by the following formula.
                                                                        r                ch                            =                            ⁢                              V                                  I                  d                                                                                                        =                            ⁢                                                (                                                            L                      g                                        -                                          Δ                      ⁢                                                                                          ⁢                                              L                        j                                                                              )                                ·                                                      [                                          μ                      ·                                              C                                                  0                          ⁢                          x                                                                    ·                      W                      ·                                              (                                                                              V                            g                                                    -                                                      V                            th                                                    -                                                      V                            2                                                                          )                                                              ]                                                        -                    1                                                                                                          (        1        )            
Note that V expresses an external drain voltage (a voltage applied to the drain electrode of the FET), Id express a current which flows in the FET, Lg and Δ Lj express a designed length of a channel forming region, and the sum of lengths of diffusions of a source region and a drain region in a horizontal direction, respectively. And μ, Cox, and W express a mobility of the FET, a capacitance of the gate insulating film, and a width of the channel forming region, respectively. And Vg and Vth express an external gate voltage (a voltage applied to the gate electrode of the FET) and a threshold voltage of the FET.
In addition, a total resistance value (Rch) of a current path in the FET is a sum of the resistance values of the channel forming region (rch) and the external resistance (r).Rch=rch+r  (2)
As shown by Expression (1), regardless of the external gate voltage (Vg), rch=0 at the time of Lg=Δ Lj due to the absence of an effective channel length. In this condition. Rch is equal to the external resistance (r) as shown in Expression (2). Thus, if Δ Lj and r do not have dependencies for the external gate voltage, rch−Lg plots for arbitrary gate voltages intersect at one point as shown in FIG. 8A. And Δ Lj is given by the x-coordinate of the intersection point and r is given by the y-coordinate thereof. However, this method cannot be applied to an FET having an LDD structure, because rch−Lg plots do not intersect at one point as shown in FIG. 8B. Thus, this method cannot be applied to an FET having an LDD structure. This is because the LDD resistance value in the external resistance changes depending on the external gate voltage and a length which is considered as a portion of the channel forming region also changes depending on the external gate voltage. Accordingly, there has been difficulty in estimating an LDD resistance value until now.
There is a method for estimating an LDD resistance value by measuring a sheet resistance of a dedicated TEG (Test Element Group), which is manufactured under the same conditions as the LDD region with respect to the dose amount and the activation method. However, the sheet resistance value obtained by this method is merely a film resistance value and is different from the LDD resistance value of a real FET. The LDD resistance of an FET is a junction resistance and changes depending upon the external gate voltage.
Further, a TEG for measuring a sheet resistance value is extremely large as compared with an LDD region in an FET in order to be accurate by a well-known method. Accordingly, the measured resistance value is the average value in a large region, and it is difficult to evaluate variations of resistance values of LDD regions in each of plural FETS.